In high-voltage applications such as motors, ballasts, dual-inductor single-capacitor converters (LLC) and cold cathode fluorescent lamp (CCFL), it is required to convert certain logic signals from low voltage to high voltage in order to control the high-voltage components. For example, in a floating gate driver circuit as shown in FIG. 1, control signals UG and LG are used to switch serially connected power switches PSW1 and PSW2 between a high-voltage terminal VH and a ground terminal GND. The direct-current (DC) input voltage VH is very high, maybe up to 300-600V or above, while the control signals UG and LG are generated by a logic circuit with reference to ground, and thus the control signal UG for the high-side power switch PSW1 must be shifted to an appropriate level. This level shift is accomplished by using a pulse generator 10 responsive to the control signal UG to generate short-pulse signals Set and Reset for a level shifter 12 to control its output voltages V1 and V2, through inverters 15 and 16 respectively, to control a bistable circuit 18, e.g. an RS flip-flop, to thereby generate a control signal Q for a driver 20 to apply a voltage OH to the control terminal of the power switch PSW1. The level shifter 12 is established with two branch circuits, one including an NMOSFET M1 to generate the voltage V1 at the output terminal AA under the control of the signal Set, and the other including an NMOSFET M2 to generate the voltage V2 at the output terminal BB under the control of the signal Reset. A resistor R1 is connected between a power supply terminal Vc and the output terminal AA to serve as the load of the NMOSFET M1, and a resistor R2 is connected between the power supply terminal Vc and the output terminal BB to serve as the load of the NMOSFET M2. Clamping circuits 13 and 14, including Zener diodes D1 and D2 respectively, are additionally shunt to the resistors R1 and R2 respectively, to clamp the voltages V1 and V2 not lower than certain values. The clamping circuits 13 and 14 may be implemented by other components or circuits alternatively. The bistable circuit 18 uses the inverted signals of the voltages V1 and V2 as its set signal S and the reset signal R, respectively, to define the control signal Q. When the control signal UG is changed from logical low to logical high, the pulse generator 10 triggers the short-pulse signal Set to turn on the NMOSFET M1, thereby pulling down the voltage V1 and as a result, the output signal S of the inverter 15 is changed to a high level and triggers the control signal Q, which in turn causes the driver 20 to turn on the power switch PSW1. When the control signal UG is changed from logical high to logical low, the pulse generator 10 triggers the short-pulse signal Reset to turn on the NMOSFET M2, thereby pulling down the voltage V2 and as a result, the output signal R of the inverter 16 is changed to a high level and thus turns off the control signal Q, which in turn causes the driver 20 to turn off the power switch PSW1.
The bistable circuit 18 and the driver 20 use the voltage at the floating node S1 between the power switches PSW1 and PSW2, rather than the voltage at the ground terminal GND, as the reference potential of the circuits. The driver 20 has its positive power supply terminal 22 connected to the power supply terminal Vc, and its negative power supply terminal 24 connected to the floating node S1. Likewise, the bistable circuit 18 has its positive power supply terminal 26 connected to the power supply terminal Vc, and its negative power supply terminal 28 connected to the floating node S1. When the power switches PSW1 and PSW2 are switched, voltage variation dv/dt occurs at the floating node S1. The dv/dt noise is introduced to the power supply terminal Vc via the bootstrap capacitor Cb connected between the power supply terminal Vc and the floating node S1, and may lead to an incorrect control signal Q to turn on or off the power switch PSW1 by mistake. The erroneous switching of the power switch PSW1 is caused by parasitic capacitors C1 and C2 at the output terminals AA and BB of the level shifter 12. A transient change in the voltage Vc induces a current I1 in the resistor R1 and a current I2 in the resistor R2 that charge or discharge the parasitic capacitors C1 and C2, respectively. As a result, the voltages V1 and V2 are varied so significantly that the logic state of the set signal S and the reset signal R is changed, and an incorrect operation ensues.
U.S. Pat. No. 5,552,731 proposes an improved circuit as shown in FIG. 2, which replaces the inverters 15 and 16 shown in FIG. 1 by a pass element 30 to prevent from incorrect operation caused by the dv/dt noise. In the pass element 30, a pair of cross-coupled PMOSFETs M3 and M4 have their input terminals connected to the output terminals BB and AA of the level shifter 12, respectively, and their output terminals connected to the input terminals S and R of the bistable circuit 18, respectively, and resistors R3 and R4 serve as the loads of the PMOSFETs M3 and M4, respectively. When the NMOSFET M1 is turned on by the short-pulse signal Set, the output voltage V1 is pulled down such that the PMOSFET M3 is turned on. Consequently, the resistors R2 and R3 become a divider to divide the voltage Vc−S1, thereby pulling up the set signal S to trigger the control signal Q. When the NMOSFET M2 is turned on by the short-pulse signal Reset, the output voltage V2 is pulled down such that the PMOSFET M4 is turned on. Consequently, the resistors R1 and R4 become a divider to divide the voltage Vc−S1, thereby pulling up the reset signal R to turn off the control signal Q. In order for the set signal S to go to logic 0 sooner than the reset signal R at the time of terminating the control signal Q, the resistor R4 must have a greater resistance than the resistor R3 so that the input terminal S of the bistable circuit 18 can be discharged at a higher speed than the input terminal R. To ensure that the foregoing goal is achievable, U.S. Pat. No. 5,572,156 further provides a switch shunt to the resistor R3 and controlled by the reset signal R.
In these arts, the level shifter 12 uses the resistors R1 and R2 as the loads, and the RC response times of the resultant R1C1 network and of the R2C2 network are fixed; therefore, dynamic control is difficult to attain. The pass element 30, on the other hand, uses the resistors R3 and R4 as the loads, and thus the fixed resistances of the resistors R3 and R4 also make it difficult to filter out the dv/dt noise by dynamic control. Moreover, since both the set signal S and the reset signal R are generated by a resistor voltage divider, the resistances of the resistors R1, R2, R3 and R4 are subject to strict limitations so as to generate the set signal S and the reset signal R of the appropriate levels. This, however, reduces the flexibility in circuit design.